The reconstruction of particle tracks from hits in tracking detectors is a computationally intensive task due to the large combinatorics of detector signals. Recent efforts have proven that ML techniques can be successfully applied to the tracking problem, extending and improving the conventional methods based on feature engineering. However, complex models can be challenging to implement on heterogeneous trigger systems, integrating architectures such as field programmable gate arrays (FPGAs). Deploying the network on an FPGA is feasible but challenging and limited by its resources. An efficient alternative can employ symbolic regression (SR). We propose a novel approach that uses SR to replace a graph-based neural network. Substituting each network block with a symbolic function preserves the graph structure of the data and enables message passing. The technique is perfectly suitable for heterogeneous hardware, as it can be implemented more easily on FPGAs and grants faster execution times on CPU with respect to conventional methods. While the tracking problem is the target for this work, it also provides a proof-of-principle for the method that can be applied to many use cases.

Accelerating graph-based tracking tasks with symbolic regression

Schiavi, Carlo;Di Bello, Francesco A;
2024-01-01

Abstract

The reconstruction of particle tracks from hits in tracking detectors is a computationally intensive task due to the large combinatorics of detector signals. Recent efforts have proven that ML techniques can be successfully applied to the tracking problem, extending and improving the conventional methods based on feature engineering. However, complex models can be challenging to implement on heterogeneous trigger systems, integrating architectures such as field programmable gate arrays (FPGAs). Deploying the network on an FPGA is feasible but challenging and limited by its resources. An efficient alternative can employ symbolic regression (SR). We propose a novel approach that uses SR to replace a graph-based neural network. Substituting each network block with a symbolic function preserves the graph structure of the data and enables message passing. The technique is perfectly suitable for heterogeneous hardware, as it can be implemented more easily on FPGAs and grants faster execution times on CPU with respect to conventional methods. While the tracking problem is the target for this work, it also provides a proof-of-principle for the method that can be applied to many use cases.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11567/1255260
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