A crucial part of treating neurological disorders like Parkinson’s and epilepsy involves using Deep Brain Stimulation (DBS) systems. This paper describes a system that provides stimulation through a multipolar biphasic current source. It consists of two identical instances, one for each cerebral hemisphere, each containing five stimulators: four of them are locally connected, while the fifth is connected to an implantable pulse generator for monopolar stimulation. Each stimulator can deliver a maximum current of 12 mA with 9-bit resolution and offers passive charge balancing. Safety features include a DC blocking capacitor for electrical isolation, ensuring minimal DC current flow in case of system failure. The proposed design compensates for up to ±50% mismatch in stimulation current sinks by utilizing current sources, thereby distributing current errors in ideal proportions. The stimulator’s voltage can be adjusted up to 30V. Based on post-layout Monte Carlo simulations, the common-mode voltage variates from its nominal value only by a standard deviation σ equal to 2 mV. Thus, referring to an overall 3σ variation, the proposed topology shows a 4× improvement in anchoring the brain voltage compared to the state-of-the-art. This architecture enables concurrent recording and stimulation, minimizing the artifacts generated by stimulation.
Multipolar Stimulator for Deep Brain Stimulation With Suppression of Stimulation-Induced Common-Mode Artifacts
Shokri, Reza;Caviglia, Daniele D.;Aiello, Orazio
2025-01-01
Abstract
A crucial part of treating neurological disorders like Parkinson’s and epilepsy involves using Deep Brain Stimulation (DBS) systems. This paper describes a system that provides stimulation through a multipolar biphasic current source. It consists of two identical instances, one for each cerebral hemisphere, each containing five stimulators: four of them are locally connected, while the fifth is connected to an implantable pulse generator for monopolar stimulation. Each stimulator can deliver a maximum current of 12 mA with 9-bit resolution and offers passive charge balancing. Safety features include a DC blocking capacitor for electrical isolation, ensuring minimal DC current flow in case of system failure. The proposed design compensates for up to ±50% mismatch in stimulation current sinks by utilizing current sources, thereby distributing current errors in ideal proportions. The stimulator’s voltage can be adjusted up to 30V. Based on post-layout Monte Carlo simulations, the common-mode voltage variates from its nominal value only by a standard deviation σ equal to 2 mV. Thus, referring to an overall 3σ variation, the proposed topology shows a 4× improvement in anchoring the brain voltage compared to the state-of-the-art. This architecture enables concurrent recording and stimulation, minimizing the artifacts generated by stimulation.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.



