Integrating AutoML and FPGA Deployment: A Pipeline for Model Selection and Hardware-Aware Implementation

The increasing demand for real-time, energy-efficient machine learning (ML) models in edge and embedded scenarios highlights the limitations of traditional CPU-based inference pipelines. This work presents a pipeline that integrates Automated Machine Learning (AutoML) with High-Level Synthesis (HLS) to enable efficient deployment of ML predictors on Field-Programmable Gate Arrays (FPGAs). Using Auto-Weka for automated algorithm selection and Bayesian hyperparameter optimization, followed by model reimplementation and parameter extraction using scikit-learn and synthesis through the AMD/Xilinx Vitis HLS toolchain, the proposed workflow combines data-driven model exploration with hardware-oriented implementation. The pipeline adopts a hybrid, human-in-the-loop approach, reflecting current practical constraints in bridging heterogeneous software and hardware environments. Experimental results show up to a 9% latency reduction compared to CPU-based inference, more than a 7× throughput improvement through parallel FPGA instantiation, and more than an order of magnitude improvement in energy efficiency when evaluated in terms of energy per inference. The proposed methodology provides a reproducible and extensible workflow for integrating AutoML-based model discovery with FPGA deployment, while highlighting both the benefits of hardware acceleration and the remaining challenges in AutoML–hardware integration.